(untitled) (International Journal of Communication Systems and Network Technologies, 2021)
Binary adders are very important in digital signal processing. Adders are basic building blocks of more complex units such as multipliers, dividers, square units, etc. This paper first presents the proposal and implementation of a new adder model called the Prediction Adder (MLG Adder). The paper also presents performance of this adder in comparison to the performance of the various adders studied. This design is highly effective and has lower processing time and latency. The system was synthesized for a variety of FPGA targets using Xilinx ISE Design Suite 14.7 Commercial Edition and performance was simulated with ISIM and other tools available from Xilinx ISE Design Suite 14.7.