Comparative Review of Floating-Point Multiplier Systems
DOI:
https://doi.org/10.18486/ijcsnt/8.2.105Keywords:
Arithmetic Logic Unit, Floating-Point Multiplier, Multi-Precision Floating Point, Multiplier System, Multiplier Architecture, FPGAs in ArithmeticAbstract
This paper presents a comprehensive comparative review of existing floating point multiplier systems. The study focuses on single, double, quadruple and multi-precision floating point multiplier architectures and seeks to identify engineering techniques involved in their development. A comparison of the performance of these systems in terms of metrics such as path delay, hardware utilization and even power consumption in some cases have been carried out. Weaknesses in the systems reviewed along with possible gaps in the area of research have also been identified in this work. This paper also serves to identify several recommendations and considerations for the development of a multi-precision floating point multiplier system capable of treating with the weaknesses of multiplier systems identified.
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