VLSI Interconnect Delay and Crosstalk Models - A Review
DOI:
https://doi.org/10.18486/ijcsnt/9.2.120Keywords:
Interconnects, Lumped, Distributed, Couplings, Crosstalk, Very Large Scale Integration (VLSI)Abstract
As the technology scales down, the interconnect structures become a predominant factor in determining the overall circuit parameters like performance, reliability and cost. Coupling capacitances and interconnect delay plays an important role in deciding the behaviour of on-chip interconnects. The paper reviews various interconnect delay models and techniques adopted by different researchers to avoid crosstalk in VLSI interconnect. It has been observed that distributed RLC interconnect delay model have applications in computer-aided design for rapid time analysis, global wire sizing and estimating switching activity even at high frequencies.
References
International Technology Roadmap for Semiconductors. 2013.
Gupta A, Maheshwari V, Sharma S and Kar R. Crosstalk noise and delay analysis for high speed on-chip global RLC VLSI interconnects with mutual inductance using 90 nm process technology. In International Conference on Computing, Communication and Automation (ICCCA 2015). pp. 1215–1219. DOI: https://doi.org/10.1109/CCAA.2015.7148579
VLSI Expert. Delay interconnect delay models static. Available online.
Zhang Y, Hu X, Deutsch A, Engin AE, Buckwalter JF and Cheng CK. Prediction and comparison of high performance on-chip global interconnection. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2011; 19(7). DOI: https://doi.org/10.1109/TVLSI.2010.2047415
Zhou D, Preparata FP and Kang SM. Interconnection delay in very high-speed VLSI. IEEE Transactions on Circuits and Systems 1991; 38(7): 779–790. DOI: https://doi.org/10.1109/31.135749
Bakoglu HB. Circuits, Interconnections and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990.
Sakurai T. Closed-form expression for interconnect delay, coupling, and crosstalk in VLSI. IEEE Transactions on Electron Devices 1993; 40(1): 118–124. DOI: https://doi.org/10.1109/16.249433
Behrouzian ARB and Masoumi N. Analytical solutions for distributed interconnect models—Part I: Step input response of finite and semi-infinite lines. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2014; 22(12). DOI: https://doi.org/10.1109/TVLSI.2013.2280816
Kaushal S and Sulochana V. Delay minimization in multi-level balanced interconnect tree. International Journal of Computer Applications 2013; 72(11). DOI: https://doi.org/10.5120/12536-9023
Kahng AB, Masuko A and Muddu S. Analytical delay models for VLSI interconnects under ramp input. In Proceedings of the ACM/IEEE International Conference on Computer-Aided Design. November 1996. pp. 30–36. DOI: https://doi.org/10.1109/ICCAD.1996.568907
Kahng AB and Muddu S. An analytical delay model for RLC interconnects. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 1997; 16(12): 1507–1514. DOI: https://doi.org/10.1109/43.664231
Shi F, Wu X and Yan Z. Improved analytical delay models for RC-coupled interconnects. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2014; 22(7). DOI: https://doi.org/10.1109/TVLSI.2013.2275071
Elmore WC. The transient response of damped linear networks with particular regard to wideband amplifiers. Journal of Applied Physics 1948; 19(1): 55–63. DOI: https://doi.org/10.1063/1.1697872
Eo Y, Eisenstadt WR, Jeong JY and Kwon OK. A new on-chip interconnect crosstalk model and experimental verification for CMOS VLSI circuit design. IEEE Transactions on Electron Devices 2000; 40(1): 129–140. DOI: https://doi.org/10.1109/16.817578
Davis JA and Meindl JD. Compact distributed RLC interconnect models—Part I: Single line transient, time delay and overshoot expressions. IEEE Transactions on Electron Devices 2000; 47(11): 2068–2077. DOI: https://doi.org/10.1109/16.877168
Venkatesan R, Davis JA and Meindl JD. Compact distributed RLC interconnect models—Part III: Transient in single and coupled lines with capacitive load termination. IEEE Transactions on Electron Devices 2003; 50(4): 1081–1093. DOI: https://doi.org/10.1109/TED.2003.812507
Milter O and Kolodny A. Crosstalk noise reduction in synthesized digital logic circuit. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2003; 11(6). DOI: https://doi.org/10.1109/TVLSI.2003.817551
Chen G and Friedman EG. An RLC interconnect model based on Fourier analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2005; 24(2): 170–183. DOI: https://doi.org/10.1109/TCAD.2004.841065
Singh HP and Mehra R. Error correction and crosstalk avoidance techniques in on-chip VLSI interconnects. International Journal of Engineering Research and Technology 2012; 1(8).
Anushree and Maheshwari V. Crosstalk noise reduction using wire spacing in VLSI global interconnects. Journal of Electronic Devices 2014; 20: 1755–1760.
Singha S and Mahanti GK. Optimization of delay and energy in on-chip buses using bus encoding technique. International Journal of Computer Applications 2014; 86(12). DOI: https://doi.org/10.5120/15035-3376
Venkataramana S and Prasad NGN. Reduced on-chip codeword generation for crosstalk effect in data transmission bus. International Journal of Science, Engineering and Advance Technology 2014; 2(11).
Sathish A, Latha MM and Kishor KL. Data encoding technique for crosstalk delay reduction on fault tolerant data-bus in DSM technology. Procedia Engineering 2012. pp. 2967–2972. DOI: https://doi.org/10.1016/j.proeng.2012.06.346
Rao JV and Rao PS. Design and implementation of memory-less forbidden transition free crosstalk avoidance CODECs for on-chip buses. International Journal of Computer Science Issues 2011; 8(6): No. 1.
Singla S and Mahanti GK. Design and implementation of memory-based cross-talk reducing algorithm to eliminate worst case crosstalk in on-chip VLSI interconnects. International Journal of Soft Computing and Engineering 2012; 2(2).
Lin TW, Tu SW and Jou JY. On-chip bus encoding for power minimization under delay constraint. In IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT). April 2007. DOI: https://doi.org/10.1109/VDAT.2007.373210
Vittal A, Chen LH, Sadowaska M, Wang KP and Yang S. Crosstalk in VLSI interconnections. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 1999; 18(12). DOI: https://doi.org/10.1109/43.811330
Kreyszig E. Advanced Engineering Mathematics. 9th ed. New York, NY, USA: Wiley, 2006.
Brown JW and Churchill RV. Fourier Series and Boundary Value Problems. 4th ed. New York, NY, USA: McGraw-Hill, 1993.
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