A Novel Adder Configuration for High Efficiency
DOI:
https://doi.org/10.18486/ijcsnt/10.1.131Keywords:
Arithmetic Circuits, Binary Adders, Arithmetic Logic, FPGAs In Arithmetic, Summing CircuitsAbstract
Binary adders are very important in digital signal processing. Adders are basic building blocks of more complex units such as multipliers, dividers, square units, etc. This paper first presents the proposal and implementation of a new adder model called the Prediction Adder (MLG Adder). The paper also presents performance of this adder in comparison to the performance of the various adders studied. This design is highly effective and has lower processing time and latency. The system was synthesized for a variety of FPGA targets using Xilinx ISE Design Suite 14.7 Commercial Edition and performance was simulated with ISIM and other tools available from Xilinx ISE Design Suite 14.7.
References
Mano, M. Morris and Charles R. Kime. 1997. Logic AND Computer Design Fundamentals. Prentice Hall, New Jersey. Volume 1.
Koren, Israel. 2001. Computer Arithmetic Algorithms. 2nd Ed. A K Peters, Natick, Massachusetts. ISBM 1-56881-160-8.
Ling, Huey. 1981. High-speed Binary Adder. IBM 1. RES DEVELOP. 0 VOL. 25 0 NO. 3 0 MAY 1981 DOI: https://doi.org/10.1147/rd.252.0156
GS Tomar, Marcus L George, “Modified Binary Multiplier Architecture to Achieve Reduced Latency and Hardware Utilization”, Wireless Personal Communication, Vol.98, No.4, pp.3549-3561, 2018. DOI: https://doi.org/10.1007/s11277-017-5028-z
Chen, Chien-In Henry and Joel Yuen. 1992. An Efficient Approach to Pipeline Scheme for Concurrent Testing of VLSI Circuits. Proceedings of IEEE/ACM Design Automation. Pg 657-660. DI: 0-7803-0593-0/92. DOI: https://doi.org/10.1109/ISCAS.1992.230166
Hill, Eric L. and Mikko H. Lipasti. 2007. Transparent Mode Flip-Flops for Collapsible Pipelines. Pp 553-560. DI: 1-4244-1258-7/07. DOI: https://doi.org/10.1109/ICCD.2007.4601952
Choi, Jung Hwan, Byung Guk Kim, Aurobindo Dasgupta and Kaushik Roy. 2010. Improved Clock-Gating Control Scheme for Transparent Pipeline. Pg: 401 – 406. DI: 978-1-4244-5767-0/10. DOI: https://doi.org/10.1109/ASPDAC.2010.5419847
L. Benini and G. D. Micheli. 1996. “Automatic synthesis of low-power gated clock finite-state machines,” IEEE Trans. on CAD, vol. 15, no. 6, pp. 630–643. DOI: https://doi.org/10.1109/43.503933
Hennessey, John and David Patterson. 2003. Computer Architecture. A Quantitative Approach. 3rd ed. San Francisco: Morgan Kaufmann Publishers.
P. Babighian et al. 2005. “A scalable algorithm for RTL insertion of gated clocks based on ODCs computation,” IEEE Trans. on CAD, vol. 24, no. 1, pp. 29–42. DOI: https://doi.org/10.1109/TCAD.2004.839489
H. Jacobson. 2004. Improved clock-gating through transparent pipelining,” in Proc. of ISLPED. pp. 26–31. DOI: https://doi.org/10.1145/1013235.1013248
Panato, Alex, Sandro Silva, Flavio Wagner, Marcelo Johann, Ricardo Reis amd Sergio Bampi. 2004. Design of Very Deep Pipelined Multipliers for FPGAs. Proceedings of the Design, Automation and test in Europe Conference and Exibition Designer’s Forum (DATE’04). IEEE Boston: Computer Society. DI: 1530-1591/04.
Suryanarayana B. Tatapudi and Jose’ G. Delgado-Frias. 2005. Designing Pipelined Systems with Clock Period Approaching Pipeline Register Delay. DI: 0-7803-9197-7/05.
Jain, Anna, Baisakhy Dash, Ajit Kumar Panda and Muchharla Suresh. 2011. FPGA Design of a Fast 32-but Floating Point Multiplier Unit. DOI: https://doi.org/10.1109/ICDCSyst.2012.6188744
Li, Zheng, Haimin Chen and Xianwen Yang. 2010. A Hardware Multiplier Design of Embedded Microprocessor. DI: 978-1-4244-6943-7/10.
D. C. Michael, Y. Q. Zhang and Q. Li. 2005. Advanced Digital with the Verilog HDL etc translating, Beijing: Publishing House of Electronics Industry.
Yilmaz, Mahmut, Derek R. Hower, Sule Ozev and Daniel J. Sorin. 2006. Self-Checking and Self-Diagnosing 32-bit Microprocessor Multiplier. International Test Conference. DI: 1-4244-0292-1/06. DOI: https://doi.org/10.1109/TEST.2006.297634
Qi, Haibing, Song Sun and Jianlan Feng. 2010. A FPGA Pipelining Design Method of Gradient Adaptive Lattice Joint Processor. 2010 2nd International Asia Conference on Informatics in Control, Automation and Robotics. pg 309-312. DI: 978-1-4244-5194-4/10. DOI: https://doi.org/10.1109/CAR.2010.5456538
Mak, Terrence, Pete Sedcole, Peter Cheung and Wayne Luk. 2008. Wave-Pipelined Signaling for On-FPGA Communication. DI: 978-1-4244-2796-3/08.
Zhang, Zhe and Xiaoming Hu. 2009. A Novel Pipelining Scheme for Network-on-Chip Router. 2009 Third International Symposium on Intelligent Information Technology Application. pg. 372-375. DI: 978-0-7695-3859-4/09. DOI: https://doi.org/10.1109/IITA.2009.91
P. Bhattacharyya, “Performance Analysis of a Low-Power High-Speed Hybrid l-bit Full Adder Circuit,” IEEE Trans. VLSI, vol. 23, 2015. DOI: https://doi.org/10.1109/TVLSI.2014.2357057
H. Naseri and S. Timarchi, “Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates,” IEEE Trans. VLSI, vol. 26, no. 8, 2018. DOI: https://doi.org/10.1109/TVLSI.2018.2820999
H. E. Yantır, A. M. Eltawil and F. J. Kurdahi, “A Two-Dimensional Associative Processor,” IEEE Trans. VLSI, vol. 26, no. 9, 2018. DOI: https://doi.org/10.1109/TVLSI.2018.2827262
Ashish BAGWARI and I. KATNA, “Low Power Ripple Carry Adder Using Hybrid 1-Bit Full Adder Circuit,” 2019 11th International Conference on Computational Intellisence and Communication Networks (CICN), Honolulu, HI, USA, 2019, pp. 124 - 127. DOI: https://doi.org/10.1109/CICN.2019.8902351
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