Design Modulo Multiplier for Symmetric Key Cryptography Using HDL
DOI:
https://doi.org/10.18486/ijcsnt/11.1.143Keywords:
IDEA, Crptography, Mobile Communication, Modulo MultiplierAbstract
This paper covers the design of modulo multiplier for International Data Encryption Algorithm (IDEA) cryptography. The current era has seen an explosive growth in communications. Applications like online banking, personal digital assistants, mobile communication, smartcards, etc. have emphasized the need for security in resource constrained environments. International Data Encryption Algorithm (IDEA) cryptography serves as a perfect network security tool because of its 128 bits key sizes and high security comparable to that of other algorithms. However, to match the ever increasing requirement for speed in today’s applications, hardware acceleration of the cryptographic algorithms is a necessity.
References
Zimmermann R, Curiger A, Bonnenberg H et al. A 177 Mb/s VLSI implementation of the International Data Encryption Algorithm. IEEE Journal of Solid-State Circuits 1994; 29: 303–307. DOI: https://doi.org/10.1109/4.278352
Lai X and Massey JL. A proposal for a new block encryption standard. In: Advances in Cryptology – EUROCRYPT ’90. Berlin, Germany: Springer-Verlag, pp. 389–404. DOI: https://doi.org/10.1007/3-540-46877-3_35
Ranjan R and Poonguzhali I. VLSI implementation of IDEA encryption algorithm. In: Mobile and Pervasive Computing (CoMPC 2008).
Modugu R, Kim YB and Choi M. A fast low-power modulo 2ⁿ + 1 multiplier. IET Computers & Digital Techniques 2011.
Timarchi S and Navi K. Improved modulo 2ⁿ + 1 adder design. International Journal of Computer and Information Engineering 2008; 2(7).
Hämäläinen A, Tommiska M and Skyttä J. 6.78 gigabits per second implementation of the IDEA cryptographic algorithm. Springer-Verlag, pp. 760–769. DOI: https://doi.org/10.1007/3-540-46117-5_78
Leong MP, Cheung OYH, Tsoi KH et al. A bit-serial implementation of the International Data Encryption Algorithm (IDEA). IEEE, 2000. DOI: https://doi.org/10.1007/3-540-44709-1_28
Kitsos P, Sklavos N, Galanis MD et al. 64-bit block ciphers: hardware implementations and comparison analysis. Elsevier 2004: 593–604. DOI: https://doi.org/10.1016/j.compeleceng.2004.11.001
Modugu R, Kim YB and Choi M. Design and performance measurement of efficient IDEA cryptohardware using novel modular arithmetic components. In: 2010 IEEE Instrumentation and Measurement Technology Conference (I2MTC), pp. 1222–1227. DOI: https://doi.org/10.1109/IMTC.2010.5488049
Thaduri M, Yoo S and Gaede R. An efficient implementation of IDEA encryption algorithm using VHDL. Elsevier 2004. DOI: https://doi.org/10.1016/j.micpro.2004.06.002
Michalski A, Gaj K and El-Ghazawi T. An implementation comparison of an IDEA encryption cryptosystem on two general-purpose reconfigurable computers.
Dharmapurikar S and Lockwood J. Fast and scalable pattern matching for network intrusion detection systems. IEEE Journal on Selected Areas in Communications 2006; 24: 1781–1792. DOI: https://doi.org/10.1109/JSAC.2006.877131
Chiranth E, Chakravarthy HVA, Naga Mohana Reddy P et al. Implementation of RSA cryptosystem using Verilog. International Journal of Scientific & Engineering Research 2011; 2(5).
Shirali M, Tefke T, Staudemeyer RC et al. A survey on anonymous communication systems with a focus on dining cryptographers networks. IEEE Access 2023; 4: 1–30. DOI: https://doi.org/10.1109/ACCESS.2023.3242870
Meraouche I, Dutta S, Tan H et al. Neural networks-based cryptography: a survey. IEEE Access 2021; 9: 124727–124740. DOI: https://doi.org/10.1109/ACCESS.2021.3109635
Pelosi G, Selleri S and Florence. A leap in cryptography: the Leon Battista Alberti cipher disk. IEEE 2021: 7–11. DOI: https://doi.org/10.1109/HISTELCON52394.2021.9787316
Gabriel A, Camargo M, Monticolo D et al. Improving the IDEA evaluation process in creative workshops through contextualization. Journal of Cleaner Production 2016; 135: 1503–1513. DOI: https://doi.org/10.1016/j.jclepro.2016.05.039
Huang QX, Yap WL, Chiu MY et al. Privacy-preserving deep learning with learnable image encryption on medical images. IEEE Access 2022; 10: 66345–66355. DOI: https://doi.org/10.1109/ACCESS.2022.3185206
Almasri O and Jani HM. Introducing an encryption algorithm based on IDEA. International Journal of Science and Research (IJSR) 2013; 2(9): 334–339.
Javed Y, Khan AS, Qahar A et al. Preventing DoS attacks in IoT using AES. Journal of Telecommunication, Electronic and Computer Engineering 2017; 9(3-11): 55–60.
Revathi Bai P and Sarala B. System-on-chip implementation of pipelined-based Advanced Encryption Standard and rand shifter for secure memory. Journal of Engineering Physics 2021; 12(10): 134–141.
Hämäläinen P, Alho T, Hännikäinen M et al. Design and implementation of low-area and low-power AES encryption hardware core. Tampere University of Technology, Institute of Digital and Computer Systems, pp. 1–7.
Tomar GS and George ML. Modified binary multiplier architecture to achieve reduced latency and hardware utilization. Wireless Personal Communications 2018; 98(4): 3549–3561. DOI: https://doi.org/10.1007/s11277-017-5028-z
Zodpe H and Sapkal A. An efficient AES implementation using FPGA with enhanced security features. Journal of King Saud University – Engineering Sciences 2020; 32: 115–122. DOI: https://doi.org/10.1016/j.jksues.2018.07.002
Smekal D, Hajny J and Martinasek Z. Comparative analysis of different implementations of encryption algorithms on FPGA network cards. IFAC-PapersOnLine 2018; 51(6): 312–317. DOI: https://doi.org/10.1016/j.ifacol.2018.07.172
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