Routing Algorithm for Symmetric Rearrangeable Networks and Emerging Applications

Authors

DOI:

https://doi.org/10.18486/ijcsnt/2.1.016

Keywords:

Rearrangeable Networks, Permutation, Interconnection Networks, Routing Tags, Complexity

Abstract

Routing algorithms for symmetric rearrangeable networks have been discussed in greater detail in the literature. Major focus of these algorithms was on designing algorithms for full occupancy networks. One of the major issues with those algorithms was the required time to setup a switch of size N. Very little effort have been put to design algorithms which compromise between time complexity and switch throughput. In this paper we propose a new routing algorithm that uses two different routing methods in routing from input stage to output stage. One of the methods is called deterministic or optimal routing and other one is called adaptive routing. Deterministic method assures that each input request will have a definite path in the network and adaptive method makes sure that the path establishment takes place as fast as possible. This new algorithm works for both full and partial permutations without any modifications to the method. An optimal routing algorithm is used in the outermost stages of the network and in the innermost stages the decision making is based on the state of the switching elements. This new algorithm is called as hybrid routing algorithm. The required execution time of this new algorithm is much faster than optimal algorithm, and it has better scaling properties than suboptimal routing algorithms. This paper also addresses some of the emerging applications built using symmetric rearrangeable network class.

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Published

2013-04-30

How to Cite

Routing Algorithm for Symmetric Rearrangeable Networks and Emerging Applications. (2013). International Journal of Communication Systems and Network Technologies, 2(1), 01-10. https://doi.org/10.18486/ijcsnt/2.1.016