Novel Binary Multiplier Architecture for Floating-Point Single Precision Multiplier
DOI:
https://doi.org/10.18486/ijcsnt/13.2.181Keywords:
Arithmetic Circuits, Binary Multiplier, Arithmetic Logic, FPGAs in ArithmeticAbstract
In this paper a novel architecture of a binary multiplier is developed to be used in implementation of floating point multipliers. The proposed architecture can be configured to operate in at 1-bit to 23-bit mode at the moment. The system also performs most operations only when a non-zero bit of the multiplier is found and as such the more non-zero bits found, the greater the number of cycles required to complete the multiplication process. The results of the testing of this system indicates that it correctly multiplies its inputs and also the latency of the 8-bit version of this system is shorter than several other versions implemented by other researchers.
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