Improved 24-bit Binary Multiplier Architecture for use in Single Precision Floating Point Multiplication
DOI:
https://doi.org/10.18486/ijcsnt/7.2.093Keywords:
Arithmetic Logic Unit, Arithmetic Circuits, Binary Multiplier, Floating-Point Multiplier, Arithmetic Logic, FPGAs in ArithmeticAbstract
Arithmetic Logic Units (ALUs) are very important components of processors performing arithmetic operations such as multiplication, division, addition, subtraction, cubing and squaring. Of all operations, multiplication is most frequently used in ALUs. Floating point multiplication is a very important component of many engineering applications such as signal processing, video processing and image processing. The dynamic range of numbers represented by floating point arithmetic is very large when compared to fixed point numbers of the same bit-width. This paper presents the development of a novel 24-bit binary multiplier architecture for use in implementation of a single precision floating point multiplier for use in data intensive applications, requiring low delay benefits. The system was synthesized for a variety of FPGA targets using Xilinx ISE Design Suite 14.7 Commercial Edition and performance was simulated with ISIM which was available from Xilinx ISE Design Suite 14.7. The implemented system was compared with existing implementations of 8-bit, 16-bit and 24-bit binary multipliers in terms of path delay. The novel 24-bit binary multiplier architecture achieved shorter path delay than its existing counterpaths.
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